IRIS

LOGHI, Mirko

LOGHI, Mirko  

DPIA - DIPARTIMENTO POLITECNICO DI INGEGNERIA E ARCHITETTURA  

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Risultati 1 - 20 di 45 (tempo di esecuzione: 0.026 secondi).
Titolo Data di pubblicazione Autore(i) File
A cosimulation methodology for HW/SW validation and performance estimation 1-gen-2009 Fummi, F; Loghi, Mirko; Poncino, M.; Pravadelli, G.
A Portable 3-D Imaging FMCW MIMO Radar Demonstrator With a 24x24 Antenna Array for Medium-Range Applications 1-gen-2017 Ganis, Alexander; Navarro, Enric Miralles; Schoenlinner, Bernhard; Prechtel, Ulrich; Meusling, Askold; Heller, Christoph; Spreng, Thomas; Mietzner, Jan; Krimmer, Christian; Haeberle, Babette; Lutz, Steffen; Loghi, Mirko; Belenguer, Angel; Esteban, Hector; Ziegler, Volker
A system concept for a 3D real-Time OFDM MIMO radar for flying platforms 1-gen-2016 Ganis, ALEXANDER RUDOLF; Miralles, Enric; Heller, Christoph; Prechtel, Ulrich; Meusling, Askold; Feldle, Heinz Peter; Loghi, Mirko; Ellinger, Frank; Ziegler, Volker
Adiabatic Spiking Neurons and Synapses for Ultra-Low Energy Neuromorphic Computing 1-gen-2023 Massarotto, M.; Saggini, S.; Loghi, M.; Esseni, D.
Aging effects of leakage optimizations for caches 1-gen-2010 Calimera, A; Loghi, Mirko; Macii, E; Poncino, M.
Aging-Aware Caches with Graceful Degradation of Performance 1-gen-2012 Mahmood, H; Loghi, Mirko; Macii, E; Poncino, M.
Analyzing On-Chip Communication in a MPSoC Environment 1-gen-2004 Loghi, Mirko; Angiolini, F; Bertozzi, D; Benini, L; Zafalon, R.
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor 1-gen-2004 Loghi, Mirko; Poncino, M; Benini, L.
Application-specific memory partitioning for joint energy and lifetime optimization. 1-gen-2012 Mahmood, H; Poncino, M; Loghi, Mirko; Macii, E.
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking 1-gen-2010 Loghi, Mirko; Golubeva, O; Macii, E; Poncino, M.
Architectural leakage-aware management of partitioned scratchpad memories 1-gen-2007 Golubeva, O; Loghi, Mirko; Poncino, M; Macii, E.
Autotuning technique for digital constant on-time controllers 1-gen-2014 Saggini, Stefano; Loghi, Mirko; Zambetti, O.; Zafarana, A.; Corradini, L.
Buffering of frequent accesses for reduced cache aging 1-gen-2011 Calimera, A; Loghi, Mirko; Macii, E; Poncino, M.
Cache coherence tradeoffs in shared-memory MPSoCs 1-gen-2006 Loghi, Mirko; Poncino, M; Benini, L.
Caorle 1 Shipwreck (II-I B.C.). The ongoing project for a remote protection of the site 1-gen-2023 Capulli, Massimo; Asta, Alessandro; Furlani, Stefano; Loghi, Mirko
Cycle-accurate power analysis for multiprocessor systems-on-a-chip 1-gen-2004 Loghi, Mirko; Poncino, M; Benini, L.
Dynamic and Formal Verification of Embedded Systems: A Comparative Survey 1-gen-2005 Loghi, Mirko; Margaria, T; Pravadelli, G; Steffen, B.
Dynamic indexing: concurrent leakage and aging optimization for caches 1-gen-2010 Calimera, A; Loghi, Mirko; Macii, E; Poncino, M.
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 1-gen-2014 Calimera, A; Loghi, Mirko; Macii, E; Poncino, M.
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support 1-gen-2007 Poletti, F; Poggiali, A; Bertozzi, D; Benini, L; Marchal, P; Loghi, Mirko; Poncino, M.