SETTINO, Francesco
SETTINO, Francesco
DPIA - DIPARTIMENTO POLITECNICO DI INGEGNERIA E ARCHITETTURA
Chip/Package/Board Co-Simulation Methodology for Crosstalk between DC/DC Converter and ADC Input Channels
2018-01-01 Settino, Francesco; Brandtner, Thomas; Subotskaya, Volha; Levanto, Antonio; Faricelli, Marco; Praemassing, Frank; Ricca, Luca Della; Koffler, Harald; Palestri, Pierpaolo; Crupi, Felice
Digital and analog TFET circuits: Design and benchmark
2018-01-01 Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Esseni, D.; Selmi, L.
Package Design Methodology for Crosstalk Mitigation between DC/DC Converter and ADC Analog Inputs in Complex SoC
2019-01-01 Settino, Francesco; Brandtner, Thomas; Niederl, Josef; Praemassing, Frank; Koffler, Harald; Palestri, Pierpaolo; Crupi, Felice
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs
2017-01-01 Settino, F.; Strangio, S.; Lanuzza, M.; Crupi, F.; Palestri, P.; Esseni, D.
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits
2017-01-01 Settino, Francesco; Lanuzza, Marco; Strangio, Sebastiano; Crupi, Felice; Palestri, Pierpaolo; Esseni, David; Selmi, Luca
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Chip/Package/Board Co-Simulation Methodology for Crosstalk between DC/DC Converter and ADC Input Channels | 1-gen-2018 | Settino, Francesco; Brandtner, Thomas; Subotskaya, Volha; Levanto, Antonio; Faricelli, Marco; Praemassing, Frank; Ricca, Luca Della; Koffler, Harald; Palestri, Pierpaolo; Crupi, Felice | |
| Digital and analog TFET circuits: Design and benchmark | 1-gen-2018 | Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Esseni, D.; Selmi, L. | |
| Package Design Methodology for Crosstalk Mitigation between DC/DC Converter and ADC Analog Inputs in Complex SoC | 1-gen-2019 | Settino, Francesco; Brandtner, Thomas; Niederl, Josef; Praemassing, Frank; Koffler, Harald; Palestri, Pierpaolo; Crupi, Felice | |
| Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs | 1-gen-2017 | Settino, F.; Strangio, S.; Lanuzza, M.; Crupi, F.; Palestri, P.; Esseni, D. | |
| Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits | 1-gen-2017 | Settino, Francesco; Lanuzza, Marco; Strangio, Sebastiano; Crupi, Felice; Palestri, Pierpaolo; Esseni, David; Selmi, Luca |