BANDIZIOL, ANDREA

BANDIZIOL, ANDREA  

Università degli Studi di UDINE  

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Titolo Data di pubblicazione Autore(i) File
A CMOS Pixelated Nanocapacitor Biosensor Platform for High-Frequency Impedance Spectroscopy and Imaging 1-gen-2018 Widdershoven, Frans; Cossettini, Andrea; Laborde, Cecilia; Bandiziol, Andrea; van Swinderen, Peter Paul; Lemay, Serge G.; Selmi, Luca
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces 1-gen-2019 Cortiula, A.; Dazzi, M.; Marcon, M.; Menin, D.; Scapol, M.; Bandiziol, A.; Cristofoli, A.; Grollitsch, W.; Nonis, R.; Palestri, P.
A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications 1-gen-2020 Menin, Davide; Bernardi, Thomas; Cortiula, Alessio; Dazzi, Martino; Prà, Alessio De; Marcon, Mattia; Scapol, Marco; Bandiziol, Andrea; Brandonisio, Francesco; Cristofoli, Andrea; Grollitsch, Werner; Nonis, Roberto; Palestri, Pierpaolo
A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces 1-gen-2019 Menin, Davide; De Pra, Alessio; Bandiziol, Andrea; Grollitsch, Werner; Nonis, Roberto; Palestri, Pierpaolo
A TCAD-Based Methodology to Model the Site-Binding Charge at ISFET/Electrolyte Interfaces 1-gen-2015 Bandiziol, Andrea; Palestri, Pierpaolo; Pittino, Federico; Esseni, David; Selmi, Luca
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces 1-gen-2022 Cortiula, A.; Menin, D.; Bandiziol, A.; Grollitsch, W.; Nonis, R.; Palestri, P.
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation 1-gen-2021 Palestri, P.; Elnaqib, A.; Menin, D.; Shyti, K.; Brandonisio, F.; Bandiziol, A.; Rossi, D.; Nonis, R.
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers 1-gen-2019 D'Ampolo, Dylan; Bandiziol, Andrea; Menin, Davide; Grollitsch, Werner; Nonis, Roberto; Palestri, Pierpaolo
Characterization, Modeling and Design of a 10Gbps Serial Link 12-mar-2018 Bandiziol, Andrea
Design and characterization of a 9.2Gbps transceiver for automotive microcontroller applications with 8-taps FFE and 1-tap unrolled/4-taps DFE 1-gen-2018 Bandiziol, A.; Grollitsch, W.; Steffan, G.; Nonis, R.; Palestri, P.
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm 1-gen-2018 Bandiziol, Andrea; Grollitsch, Werner; Brandonisio, Francesco; Bassi, Matteo; Nonis, Roberto; Palestri, Pierpaolo
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes 1-gen-2018 Dazzi, Martino; Palestri, Pierpaolo; Rossi, Davide; Bandiziol, Andrea; Loi, Igor; Bellasi, David; Benini, Luca
System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics 1-gen-2017 Bandiziol, Andrea; W., Grollitsch; F., Brandonisio; R., Nonis; Palestri, Pierpaolo