Accurate Cyclic Synchronization on Bandwidth-Limited Data Links for Hard Paralleling of Power Electronic Converters

Modularized power electronics systems, designed to flexibly scale power and voltage ranges by parallelizing and/or stacking of multiple units, represent a fundamental research and industrial field. Hard parallelization of multiple power modules normally requires tight synchronization of the PWM signals, especially for converters with high switching frequency adopting wide-bandgap devices. Challenging prevailing assumptions, where an accurate synchronization requires global shared clocks and high bandwidth interfaces, an alternative approach, based on payload injection on 100 Mbit/s Ethernet is proposed and discussed in this paper. Synchronization of the primary-and secondary-sides of a bidirectional isolated DC transformer (DCX) based on CLLC resonant topology and controlled by FPGAs, is considered as a case study. It is shown that for this approach, the jitter accuracy mainly depends on the time resolution of the counters involved, given that additional jitter sources are reduced to a minimum. The proposed method supports point-to-point configurations while achieving a jitter down to ±2.0 ns, which can be daisy-chained over multiple nodes, albeit with increasing jitter at each hop.