High-resolution digital pulse-width-modulation (HRDPWM) is essential for fast-switching power electronics applications. This work presents a novel hybrid method that combines the Serializer/Deserializer (SERDES) primitive, operated at double data rate (DDR) with deterministic clock-phase-switching. This achieves sub-nanosecond resolution without the need for asynchronous delay elements, while allowing the counter logic to operate at comparably low frequencies. The architecture is robust to process-voltage-temperature (PVT) variations by design and has been validated on AMD/Xilinx Artix-7 and UltraScale+ devices. A use case demonstrator is considered to prove the effectiveness of the proposed solution, based on a 1MHz synchronous buck converter, being part of a 48V to 1V sigma-converter. Experimental results proved that the measured timing resolution was as low as 227 ps, with good linearity of duty cycle steps (R2 > 0.99996) and low jitter. Even though the individual performance factors are not the peak in literature, the focus was high-class performance across all categories for standard implementation architectures, and fulfilling the reasonable needs of current converter topologies.
Hybrid High-Resolution Digital PWM Based on SERDES & Clock-Phase-Switching Methods
Petrella R.
2026-01-01
Abstract
High-resolution digital pulse-width-modulation (HRDPWM) is essential for fast-switching power electronics applications. This work presents a novel hybrid method that combines the Serializer/Deserializer (SERDES) primitive, operated at double data rate (DDR) with deterministic clock-phase-switching. This achieves sub-nanosecond resolution without the need for asynchronous delay elements, while allowing the counter logic to operate at comparably low frequencies. The architecture is robust to process-voltage-temperature (PVT) variations by design and has been validated on AMD/Xilinx Artix-7 and UltraScale+ devices. A use case demonstrator is considered to prove the effectiveness of the proposed solution, based on a 1MHz synchronous buck converter, being part of a 48V to 1V sigma-converter. Experimental results proved that the measured timing resolution was as low as 227 ps, with good linearity of duty cycle steps (R2 > 0.99996) and low jitter. Even though the individual performance factors are not the peak in literature, the focus was high-class performance across all categories for standard implementation architectures, and fulfilling the reasonable needs of current converter topologies.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
