This paper proposes a time-optimal digital controller for the phase-shedding in multi-phase buck converters. Phase shedding is an established technique to improve the efficiency of multi-phase converters at light load, by changing the active number of phases depending on the load current level. In order to minimize the output voltage deviation due to phase shedding and the transient time required to recover the nominal operating conditions, a minimum time algorithm is investigated. The proposed technique is insensitive to the power stage parameters, as its operation relies only on the steady-state duty-cycle and the number of phases to be turned-on or turned-off. The minimum response time is achieved through a feedforward action undertaken as soon as the phase shedding command is received. The proposed approach is validated through experimental tests on a synchronous buck converter prototype. For the purpose of rapid-prototyping, the proposed digital controller is implemented in FPGA.

FPGA implementation of phase shedding with time-optimal controller in multi-phase buck converters

Mattavelli P.;Saggini S.
2009

Abstract

This paper proposes a time-optimal digital controller for the phase-shedding in multi-phase buck converters. Phase shedding is an established technique to improve the efficiency of multi-phase converters at light load, by changing the active number of phases depending on the load current level. In order to minimize the output voltage deviation due to phase shedding and the transient time required to recover the nominal operating conditions, a minimum time algorithm is investigated. The proposed technique is insensitive to the power stage parameters, as its operation relies only on the steady-state duty-cycle and the number of phases to be turned-on or turned-off. The minimum response time is achieved through a feedforward action undertaken as soon as the phase shedding command is received. The proposed approach is validated through experimental tests on a synchronous buck converter prototype. For the purpose of rapid-prototyping, the proposed digital controller is implemented in FPGA.
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11390/860839
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 11
  • ???jsp.display-item.citation.isi??? ND
social impact