statistiche ricercatore

Continente	#
NA - Nord America	2.980
AS - Asia	425
EU - Europa	405
Continente sconosciuto - Info sul continente non disponibili	72
SA - Sud America	50
AF - Africa	4
Totale	3.936

Nazione	#
US - Stati Uniti d'America	2.971
SG - Singapore	190
IT - Italia	130
CN - Cina	112
UA - Ucraina	75
DE - Germania	45
HK - Hong Kong	39
BR - Brasile	38
SE - Svezia	31
RU - Federazione Russa	25
FI - Finlandia	23
GB - Regno Unito	21
TR - Turchia	21
FR - Francia	19
IN - India	17
VN - Vietnam	17
IE - Irlanda	13
JP - Giappone	8
AT - Austria	6
PH - Filippine	6
MX - Messico	5
BD - Bangladesh	3
CH - Svizzera	3
CO - Colombia	3
EC - Ecuador	3
VE - Venezuela	3
AR - Argentina	2
BG - Bulgaria	2
CA - Canada	2
GR - Grecia	2
IQ - Iraq	2
RO - Romania	2
SA - Arabia Saudita	2
ZA - Sudafrica	2
AE - Emirati Arabi Uniti	1
BB - Barbados	1
BE - Belgio	1
BN - Brunei Darussalam	1
EE - Estonia	1
EG - Egitto	1
ES - Italia	1
EU - Europa	1
GE - Georgia	1
GF - Guiana Francese	1
HR - Croazia	1
ID - Indonesia	1
LT - Lituania	1
MA - Marocco	1
MY - Malesia	1
NL - Olanda	1
PK - Pakistan	1
PL - Polonia	1
PR - Porto Rico	1
QA - Qatar	1
RS - Serbia	1
TH - Thailandia	1
XK - ???statistics.table.value.countryCode.XK???	1
Totale	3.866

Nome	#
Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells	1.674
Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain	215
Early assessment of tunnel-FET for energy-efficient logic circuits	202
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits	192
Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits	190
Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations	189
Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs	188
Experimental characterization of the Static Noise Margins of strained Silicon complementary Tunnel-FET SRAM	175
Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits	173
Performance analysis of different SRAM cell topologies employing tunnel-FETs	167
Digital and analog TFET circuits: Design and benchmark	157
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders	145
Mixed device-circuit simulations of 6T/8T SRAM cells employing tunnel-FETs	138
Experimental examination of tunneling paths in SiGe/Si gate-normal tunneling field-effect transistors	131
Totale	3.936

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2021/2022	144	0	0	13	6	3	8	9	3	2	19	61	20
2022/2023	260	15	26	2	47	23	61	0	31	33	2	18	2
2023/2024	49	9	2	3	0	7	11	5	5	2	3	0	2
2024/2025	1.692	1.333	170	20	7	2	10	11	22	17	5	37	58
2025/2026	371	28	42	20	15	62	33	80	9	31	31	8	12
2026/2027	76	20	30	26	0	0	0	0	0	0	0	0	0
Totale													3.936