CORTIULA, ALESSIO
CORTIULA, ALESSIO
DPIA - DIPARTIMENTO POLITECNICO DI INGEGNERIA E ARCHITETTURA
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A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces
2022-01-01 Cortiula, A.; Menin, D.; Bandiziol, A.; Grollitsch, W.; Nonis, R.; Palestri, P.
Comparison Between NRZ, PAM-3, PAM-4 and Duobinary Modulation in High-Speed Serial Interfaces
2025-01-01 Cortiula, A.; Danelutti, M.; Menin, D.; Bandiziol, A.; Driussi, F.; Palestri, P.
Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS
2025-01-01 Cortiula, A.; Scubla, D.; Murra, S.; Menin, D.; Bandiziol, A.; Driussi, F.; Palestri, P.
Modeling of Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4 Serial Interfaces
2025-01-01 Cortiula, Alessio; Menin, Davide; Bandiziol, Andrea; Driussi, Francesco; Palestri, Pierpaolo
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces | 1-gen-2022 | Cortiula, A.; Menin, D.; Bandiziol, A.; Grollitsch, W.; Nonis, R.; Palestri, P. | |
| Comparison Between NRZ, PAM-3, PAM-4 and Duobinary Modulation in High-Speed Serial Interfaces | 1-gen-2025 | Cortiula, A.; Danelutti, M.; Menin, D.; Bandiziol, A.; Driussi, F.; Palestri, P. | |
| Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS | 1-gen-2025 | Cortiula, A.; Scubla, D.; Murra, S.; Menin, D.; Bandiziol, A.; Driussi, F.; Palestri, P. | |
| Modeling of Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4 Serial Interfaces | 1-gen-2025 | Cortiula, Alessio; Menin, Davide; Bandiziol, Andrea; Driussi, Francesco; Palestri, Pierpaolo |