Modeling of Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4 Serial Interfaces

We have employed a time-domain behavioral simulator to analyze how different design options for bang-bang Clock and Data Recovery (CDR) impact the Jitter Tolerance (JTOL) performance of High-Speed Serial Interfaces (HSSIs) with PAM-4 signaling. The simulator includes the effect of Inter-Symbol Interference (ISI) due to the transmission channel, various equalization schemes and a detailed description of the CDR architecture. Many design options have been investigated, with particular focus on transition filtering and on the algorithm to identify the Early/Late (E/L) information from data and edge samples after deserialization. It has been found that if majority voting is employed to derive a single set of E/L information from an array of phase detectors working on deserialized data and edges, the different filtering strategies provide the same JTOL, meaning that one can avoid transition filtering and furthermore use a single edge sampler with a zero threshold, significantly simplifying the CDR architecture. Instead, if summation of the E/L information from deserialized data and edges is performed, the decision to use one or three thresholds for the edge sampling and the choice of whether to implement transition filtering both impact JTOL; however, better performance is achieved under these conditions than when employing majority voting on the deserialized E/L signals.