statistiche ricercatore

Continente	#
NA - Nord America	715
AS - Asia	491
EU - Europa	249
SA - Sud America	83
Continente sconosciuto - Info sul continente non disponibili	39
AF - Africa	13
Totale	1.590

Nazione	#
US - Stati Uniti d'America	690
SG - Singapore	160
CN - Cina	99
IT - Italia	75
BR - Brasile	61
HK - Hong Kong	59
IN - India	35
VN - Vietnam	31
JP - Giappone	25
DE - Germania	23
KR - Corea	22
NL - Olanda	22
FR - Francia	17
RU - Federazione Russa	17
AT - Austria	16
TW - Taiwan	16
CA - Canada	15
SE - Svezia	14
GB - Regno Unito	13
UA - Ucraina	11
IE - Irlanda	10
AR - Argentina	9
TR - Turchia	8
BD - Bangladesh	6
BE - Belgio	6
RO - Romania	6
AE - Emirati Arabi Uniti	5
IQ - Iraq	5
MX - Messico	5
ZA - Sudafrica	5
CO - Colombia	4
EG - Egitto	4
FI - Finlandia	4
AM - Armenia	3
CH - Svizzera	3
EC - Ecuador	3
ID - Indonesia	3
NO - Norvegia	3
UZ - Uzbekistan	3
CL - Cile	2
CZ - Repubblica Ceca	2
IR - Iran	2
KE - Kenya	2
NP - Nepal	2
PL - Polonia	2
BA - Bosnia-Erzegovina	1
BM - Bermuda	1
BO - Bolivia	1
BS - Bahamas	1
BY - Bielorussia	1
CR - Costa Rica	1
ES - Italia	1
JM - Giamaica	1
KG - Kirghizistan	1
KZ - Kazakistan	1
LV - Lettonia	1
MA - Marocco	1
MD - Moldavia	1
MO - Macao, regione amministrativa speciale della Cina	1
NI - Nicaragua	1
OM - Oman	1
PH - Filippine	1
PY - Paraguay	1
SN - Senegal	1
TH - Thailandia	1
TM - Turkmenistan	1
UY - Uruguay	1
VE - Venezuela	1
Totale	1.551

Nome	#
Modelling and Design of High-Speed Wireline Transceivers with Fully-Adaptive Equalization	479
Simulation and automated characterisation of optimal load for flexible composite generators based on piezoelectric ZnO nanowires	182
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces	175
A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces	143
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers	143
A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications	141
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces	118
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation	110
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications	99
Totale	1.590

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2021/2022	57	0	0	0	0	2	1	9	2	0	10	23	10
2022/2023	116	11	18	0	12	15	18	24	6	6	1	2	3
2023/2024	177	11	23	16	13	7	17	9	20	4	17	11	29
2024/2025	283	20	19	9	12	19	30	19	29	28	33	28	37
2025/2026	486	26	71	34	53	94	31	38	20	30	34	31	24
2026/2027	118	22	20	21	47	8	0	0	0	0	0	0	0
Totale													1.590