statistiche ricercatore

Nazione	#
US - Stati Uniti d'America	612
SG - Singapore	153
CN - Cina	95
IT - Italia	69
BR - Brasile	60
HK - Hong Kong	58
IN - India	35
VN - Vietnam	31
JP - Giappone	24
DE - Germania	22
NL - Olanda	21
KR - Corea	19
FR - Francia	17
RU - Federazione Russa	17
AT - Austria	16
TW - Taiwan	15
CA - Canada	14
SE - Svezia	13
GB - Regno Unito	11
UA - Ucraina	11
IE - Irlanda	10
AR - Argentina	9
TR - Turchia	8
BD - Bangladesh	6
BE - Belgio	6
AE - Emirati Arabi Uniti	5
IQ - Iraq	5
RO - Romania	5
ZA - Sudafrica	5
FI - Finlandia	4
MX - Messico	4
AM - Armenia	3
CH - Svizzera	3
CO - Colombia	3
EG - Egitto	3
ID - Indonesia	3
NO - Norvegia	3
UZ - Uzbekistan	3
CL - Cile	2
CZ - Repubblica Ceca	2
EC - Ecuador	2
IR - Iran	2
KE - Kenya	2
NP - Nepal	2
PL - Polonia	2
BA - Bosnia-Erzegovina	1
BO - Bolivia	1
BS - Bahamas	1
BY - Bielorussia	1
ES - Italia	1
KG - Kirghizistan	1
KZ - Kazakistan	1
LV - Lettonia	1
MA - Marocco	1
MO - Macao, regione amministrativa speciale della Cina	1
NI - Nicaragua	1
PH - Filippine	1
PY - Paraguay	1
SN - Senegal	1
TH - Thailandia	1
TM - Turkmenistan	1
UY - Uruguay	1
VE - Venezuela	1
Totale	1.433

Nome	#
Modelling and Design of High-Speed Wireline Transceivers with Fully-Adaptive Equalization	431
Simulation and automated characterisation of optimal load for flexible composite generators based on piezoelectric ZnO nanowires	172
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces	169
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers	136
A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces	133
A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications	133
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces	108
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation	101
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications	89
Totale	1.472

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2020/2021	15	0	0	0	0	0	0	0	0	0	0	0	15
2021/2022	74	5	7	2	3	2	1	9	2	0	10	23	10
2022/2023	116	11	18	0	12	15	18	24	6	6	1	2	3
2023/2024	177	11	23	16	13	7	17	9	20	4	17	11	29
2024/2025	283	20	19	9	12	19	30	19	29	28	33	28	37
2025/2026	486	26	71	34	53	94	31	38	20	30	34	31	24
Totale													1.472