Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits

This paper presents a comparative study between Tunnel-FETs (TFETs) and SOI MOSFETs for ultra-low power digital circuits targeting ultra-low voltages (below 500mV). We illustrateg a device-circuit co-design of n- and p-type Tunnel FETs leading to a good tradeoff between current leakage, effective capacitance and transistor imbalance at ultra-low VDD. TFETs and MOSFETs at 30 nm gate length are compared in terms of DC robustness, effect of transistor stacking, performance and potential for minimum-energy operation under aggressive voltage scaling.