Modeling of PAM-4 high speed interfaces and design of a 64 Gb/s wireline receiver

Modern digital systems rely on extremely fast and reliable data communication links. Applications such as cloud computing, artificial intelligence, high-performance computing, and advanced automotive electronics demand ever-increasing bandwidth with strict energy and latency constraints. High-Speed Serial Interfaces (HSSIs) have therefore became fundamental building blocks, enabling multi-tens-of-gigabit data exchange between integrated circuits and across computing platforms. However, as data rates grow, system design becomes significantly more challenging. Transmission channels introduce severe frequency-dependent loss, reflections, and dispersion, resulting in strong Inter-Symbol Interference (ISI). Clock sources and on-chip circuitry contribute jitter and noise, potentially closing the eye diagram and increasing the Bit-Error Rate (BER). In this scenario, engineers must simultaneously optimize equalization, clock-and-data recovery (CDR), power consumption, and silicon area, making architectural choices complex and strongly inter-dependent. This thesis focuses on the modeling and analysis of wireline transceiver, finally leading to circuit implementation of high-speed wireline receivers employing Pulse-Amplitude Modulation with four levels (PAM-4). PAM-4 has become a key technology in modern standards such as PCIe 6.0, as it doubles the data throughput with respect to NRZ signaling at the same symbol rate—at the cost of reduced voltage margin and higher system complexity. The thesis is divided into two main parts. In the first part, a complete in-house simulation framework for serial interfaces is presented and both in terms of the preexisting version for NRZ and the newly developed extension to PAM-4. The tool combines probabilistic analysis with time-domain modeling, enabling accurate evaluation of eye diagrams, bathtub curves, and jitter tolerance. Channel modeling includes realistic transmission line effects and CTLE behavior, while equalization incorporates FFE and DFE techniques. A specific contribution of this work is the extension of the framework to support PAM-4 systems with fully adaptive algorithms for threshold (dLev) and DFE-tap estimation. Additionally, several CDR schemes are investigated, including majority voting, summation, transition filtering, and multi-threshold detection. The framework allows direct comparison between simple analytical models and simulation results, offering valuable insight into system-level trade-offs. In the second part, the methodology developed in simulation is applied to the design of a complete 64 Gb/s PAM-4 receiver inspired by the PCIe 6.0 standard and implemented in an advanced CMOS technology node. The link architecture is defined based on channel characteristics and jitter requirements extracted from the simulation environment. Key circuit blocks—including the analog front-end, comparators, DACs for threshold generation, clock-generation and phase-interpolator circuits, and digital adaptation logic—are designed, simulated, and integrated to the whole system. The results demonstrate that accurate system-level modeling is essential to guide architectural decisions and optimize circuit performance before transistor level design and design take place. The methodology developed here can support future research and commercial designs targeting data rates beyond 64 Gb/s and more advanced signaling techniques.