This paper presents a novel hysteresis phenomenon induced in the latch-up I-V characteristics of CMOS structures by three dimensional effects producing strongly bias dependent non-uniformities in the current lateral distribution. This behavior has been experimentally reproduced in a lumped element circuit, and a suitable model is presented.

Three dimensional distribution of Latchup current in scaled CMOS structures

SELMI, Luca;SANGIORGI, Enrico;
1987-01-01

Abstract

This paper presents a novel hysteresis phenomenon induced in the latch-up I-V characteristics of CMOS structures by three dimensional effects producing strongly bias dependent non-uniformities in the current lateral distribution. This behavior has been experimentally reproduced in a lumped element circuit, and a suitable model is presented.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11390/682425
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