This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators.

LC-Oscillator featuring independent Gate biasing implemented in 32 nm CMOS technology

PONTON, Davide;PALESTRI, Pierpaolo;SELMI, Luca
2010-01-01

Abstract

This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators.
2010
9781424458165
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11390/884123
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