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Sfoglia per Rivista  IEEE ELECTRON DEVICE LETTERS

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Mostrati risultati da 1 a 20 di 26
Titolo Data di pubblicazione Autore(i) File
"A Novel Method to Characterize Parasitic Capacitances in MOSFET's" 1-gen-1995 B., Ricco'; Esseni, David
Channel-Length Dependence of Low-Field Mobility in Silicon-Nanowire FETs 1-gen-2009 Poli, S; Pala, M
"Characterization of Polysilicon-Gate Depletion in MOS Structures" 1-gen-1996 B., Riccò; R., Versari; Esseni, David
Energy minimization and Kirchhoff’s laws in Negative Capacitance Ferroelectric Capacitors and MOSFETs 1-gen-2017 Rollo, Tommaso; Esseni, David
Evidence of Substrate Enhanced High Energy Tails in the Distribution Function of Deep Submicron MOSFETs by Light Emission Measurements 1-gen-1999 Pavesi, M; Selmi, Luca; Manfredi, M; Sangiorgi, Enrico; Mastrapasqua, M; Bude, J.
Full-Band Quantization Analysis Reveals a Third Valley in Silicon Inversion Layers 1-gen-2005 Esseni, David; Palestri, Pierpaolo
Hot Hole Gate Current in Surface Channel p-MOSFETs 1-gen-2001 Driussi, Francesco; Esseni, David; Selmi, Luca; Piazza, F.
Hot-Electron induced Photon Energies in n-channel MOSFET’s operating at 77 and 300 K 1-gen-1989 Lanzoni, M; Manfredi, M; Selmi, Luca; Sangiorgi, Enrico; Cappelletti, R; Ricco, B.
Hysteresis cycle in the Latch-up characteristic of wide CMOS structures 1-gen-1988 Selmi, Luca; Sangiorgi, Enrico; Crisenza, G; Re, D; Ricco, B.
Impact of band structure on charge trapping in thin SiO2/Al2O3/Poly-Si gate stacks 1-gen-2004 L., Pantisano; Lucci, Luca; E., Cartier; A., Kerber; G., Groeseneken; M., Green; Selmi, Luca
Influence of interface traps on ferroelectric NC-FETs 1-gen-2018 Rollo, Tommaso; Esseni, David
Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors 1-gen-2013 Knoll, L; Zhao, Q. J.; Nichau, A; Trellenkamp, S; Richter, S; Schäfer, A; Esseni, David; Selmi, Luca; Bourdelle, K. K.; Mantl, S.
Large On-Current Enhancement in Hetero-Junction Tunnel-FETs via Molar Fraction Grading 1-gen-2014 Sylvan, Brocard; Marco G., Pala; Esseni, David
Minimizing thermal resistance and collector-to-substrate capacitance in graded base SiGe BiCMOS on SOI 1-gen-2002 M., Mastrapasqua; Palestri, Pierpaolo; A., Pacelli; G. K., Celler; M. R., Frei; P. R., Smith; R. W., Johnson; L., Bizzarro; W., Lin; T. G., Ivanov; M. S., Carroll; I. C., Kizilyalli; C. A., King
Mobility simulation of a novel Si/SiGe FET structure 1-gen-1996 Abramo, Antonio; J., Bude; F., Venturi; M. R., Pinto
Monte Carlo Simulation of Impact Ionization in SiGe HBTs 1-gen-2001 Palestri, Pierpaolo; Pacelli, A.; Mastrapasqua, M.; Bude, J. D.
New design perspective for Ferroelectric NC-FETs 1-gen-2018 Rollo, Tommaso; Esseni, David
Non-Local Effects in p-MOSFET Substrate Hot Hole Injection Experiments 1-gen-1995 Selmi, Luca; Sangiorgi, Enrico; Bez, R.
"Non-scaling of MOSFETs Linear Resistance in the Deep Sub-micron Regime" 1-gen-1998 Esseni, David; H., Iway; M. SAITO AND B., Ricco
On the Apparent Mobility in Nanometric n-MOSFETs 1-gen-2007 Zilli, M; Esseni, David; Palestri, Pierpaolo; Selmi, Luca
Mostrati risultati da 1 a 20 di 26
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