Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher oncurrents of n- and p-TFETs of >10 μA/μm at VDS = 0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very low VDD = 0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD = 1.0 V.

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

ESSENI, David;SELMI, Luca;
2013-01-01

Abstract

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher oncurrents of n- and p-TFETs of >10 μA/μm at VDS = 0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very low VDD = 0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD = 1.0 V.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11390/867610
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