A computational study of van der Waals tunnel transistors: fundamental aspects and design challenges

We propose a model Hamiltonian for van der Waals tunnel transistors relying on a few physical parameters that we calibrate against DFT band structure calculations. This approach allowed us to develop a fully threedimensional (3-D) NEGF based simulator and to investigate fundamental and design aspects related to van der Waals tunnel transistors, such as: (a) area and edge tunneling components, and IDS scaling with device area; (b) impact of top gate alignment and back-oxide thickness on the device performance; (c) influence of inelastic phonon scattering on the device operation and subthreshold swing; (d) benchmarking of switching energy and delay.