Microscopic Analysis of the Impact of Substrate Bias on the Gate Current of pMOSFETs

This paper presents a detailed numerical investigation of the recently reported phenomenon of substrate enhanced hole gate current in deep submicron pMOS transistors [1]. To this purpose, full-band Monte Carlo simulations of carrier heating and injection in the gate oxide have been carried out at different substrate voltages. Results are in good qualitative agreement with previously reported measurements, and provide a clear microscopic picture to explain the experimentally observed features of electron and hole gate currents in pMOS devices.