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Design options for hetero-junction tunnel FETs with high on current and steep sub-threshold voltage slope
2013-01-01 S., Brocard; Esseni, David; M. G., Pala
Deuterium Effect on Interface States and SILC Generation in the CHE Stress Conditions: A Comparative Study
2000-01-01 Esseni, David; Bude, J.; Selmi, Luca
Development of an analytical mobility model for the simulation of uktra thin SOI MOSFETs
2003-01-01 Alessandrini, A.; Esseni, David; Fiegna, C.
Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits
2014-01-01 M., Alioto; Esseni, David
DFT study of graphene doping due to metal contacts
2019-01-01 Khakbaz, Pedram; Driussi, F.; Gambi, A.; Giannozzi, P.; Venica, S.; Esseni, D.; Gaho, A.; Kataria, S.; Lemme, M. C.
Does Multi Trap Assisted Tunneling Explain the Oxide Thickness Dependence of the Statistics of SILC in FLASH Memory Arrays ?
2006-01-01 Vianello, E; Driussi, Francesco; Esseni, David; Selmi, Luca; VAN DUUREN, M; Widdershoven, F.
Drain Current Computation in Nanoscale nMOSFETs: Comparison of Transport Models
2010-01-01 Sangiorgi, E; Alexander, C; Asenov, A; AUBRY-FORTUNA, V; Baccarani, G; Bournel, A; Braccioli, M; Cheng, B; Dollfus, P; Esposito, A; Esseni, D; FENOUILLET-BERANGER, C; Fiegna, C; Fiori, G; Ghetti, A; Iannaccone, G; Martinez, A; Majkusiak, B; Monfray, S; Palestri, P; Peikert, V; Reggiani, S; Riddet, C; SAINT-MARTIN, J; Schenk, A; Selmi, L; Silvestri, L; Walczak, J; Toniutti, P
Drain Current Improvements in Uniaxially Strained p-MOSFETs: a Multi-Subband Monte Carlo Study
2008-01-01 Conzatti, Francesco; DE MICHIELIS, Marco; Esseni, David; Palestri, Pierpaolo
Early assessment of tunnel-FET for energy-efficient logic circuits
2016-01-01 Crupi, Felice; Strangio, Sebastiano; Palestri, Pierpaolo; Lanuzza, Marco; Esseni, David
Effect of the Grid Size on the Stability of Self-Consistent Monte-Carlo Simulations
2005-01-01 N., Barin; Palestri, Pierpaolo; Esseni, David; C., Fiegna
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Design options for hetero-junction tunnel FETs with high on current and steep sub-threshold voltage slope | 1-gen-2013 | S., Brocard; Esseni, David; M. G., Pala | |
| Deuterium Effect on Interface States and SILC Generation in the CHE Stress Conditions: A Comparative Study | 1-gen-2000 | Esseni, David; Bude, J.; Selmi, Luca | |
| Development of an analytical mobility model for the simulation of uktra thin SOI MOSFETs | 1-gen-2003 | Alessandrini, A.; Esseni, David; Fiegna, C. | |
| Device-circuit co-design and comparison of ultra-low voltage Tunnel-FET and CMOS digital circuits | 1-gen-2014 | M., Alioto; Esseni, David | |
| DFT study of graphene doping due to metal contacts | 1-gen-2019 | Khakbaz, Pedram; Driussi, F.; Gambi, A.; Giannozzi, P.; Venica, S.; Esseni, D.; Gaho, A.; Kataria, S.; Lemme, M. C. | |
| Does Multi Trap Assisted Tunneling Explain the Oxide Thickness Dependence of the Statistics of SILC in FLASH Memory Arrays ? | 1-gen-2006 | Vianello, E; Driussi, Francesco; Esseni, David; Selmi, Luca; VAN DUUREN, M; Widdershoven, F. | |
| Drain Current Computation in Nanoscale nMOSFETs: Comparison of Transport Models | 1-gen-2010 | Sangiorgi, E; Alexander, C; Asenov, A; AUBRY-FORTUNA, V; Baccarani, G; Bournel, A; Braccioli, M; Cheng, B; Dollfus, P; Esposito, A; Esseni, D; FENOUILLET-BERANGER, C; Fiegna, C; Fiori, G; Ghetti, A; Iannaccone, G; Martinez, A; Majkusiak, B; Monfray, S; Palestri, P; Peikert, V; Reggiani, S; Riddet, C; SAINT-MARTIN, J; Schenk, A; Selmi, L; Silvestri, L; Walczak, J; Toniutti, P | |
| Drain Current Improvements in Uniaxially Strained p-MOSFETs: a Multi-Subband Monte Carlo Study | 1-gen-2008 | Conzatti, Francesco; DE MICHIELIS, Marco; Esseni, David; Palestri, Pierpaolo | |
| Early assessment of tunnel-FET for energy-efficient logic circuits | 1-gen-2016 | Crupi, Felice; Strangio, Sebastiano; Palestri, Pierpaolo; Lanuzza, Marco; Esseni, David | |
| Effect of the Grid Size on the Stability of Self-Consistent Monte-Carlo Simulations | 1-gen-2005 | N., Barin; Palestri, Pierpaolo; Esseni, David; C., Fiegna |
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Opzioni
Scopri
Tipologia
- 4 Contributo in Atti di Convegno ... 159
- 4 Contributo in Atti di Convegno ... 159
Data di pubblicazione
- 2020 - 2023 16
- 2010 - 2019 72
- 2000 - 2009 64
- 1994 - 1999 7
Editore
- IEEE 29
- Institute of Electrical and Elect... 15
- Editions Frontieres 2
- Association for Computing Machinery 1
- DIEGM - Università degli Studi di... 1
- Springer Wien New York 1
Rivista
- ECS TRANSACTIONS 1
- MICROELECTRONIC ENGINEERING 1
- PROCEEDINGS OF THE EUROPEAN SOLID... 1
- SOLID-STATE ELECTRONICS 1
Serie
- INTERNATIONAL CONFERENCE ON SIMUL... 2
- PROCEEDINGS OF THE EUROPEAN SOLID... 2
- TECHNICAL DIGEST - INTERNATIONAL ... 2
Keyword
- Electrical and Electronic Enginee... 5
- FinFETs 4
- Electronic 3
- Field effect transistors 3
- Integrated circuit modeling 3
- Logic gates 3
- NEGF 3
- Neuromorphic Computing 3
- Optical and Magnetic Materials 3
- Scattering 3
Lingua
- eng 118
Accesso al fulltext
- reserved 96
- no fulltext 50
- partially open 6
- restricted 5
- open 2