Modelling, Simulation and Characterization of Tunnel-FET Devices for Ultra-low Power Electronics

In the last years a significant effort has been spent by the microelectronic industry to reduce the chip power consumption of the electronic systems since the latter is becoming a major limitation to CMOS technology scaling. Many strategies can be adopted to reduce the power consumption. They range from the system to the electron device level. In the last years Tunnel Field Effect Transistors (TFET) have imposed as possible candidate devices for replacing the convential MOSFET in ultra low power application at supply voltages VDD < 0.5V. TFET operation is based on a Band-to-Band Tunneling (BtBT) mechanism of carrier injection in the channel and they represent a disruptive revolutionary device concept. This thesis investigates TFET modeling and simulation, a very challenging topic because of the difficulties in modeling BtBT accurately. We present a modified Multi Subband Monte Carlo (MSMC) that has been adapted for the simulation of Planar Ultra Thin Body (UTB) Fully Depleted Semiconductor on Insulator (FD-ScOI) homo- and hetero-junction TFET implemented with arbitrary semiconductor materials. The model accounts for carrier quantization with a heuristic but accurate quantum correction validated by means of comparison with full quantum model and experimental results. The MSMC model has been used to simulate and assess the performance of idealized homo- and hetero-junction TFETs implemented in Si, SiGe alloys or InGaAs compounds. In the second part of the thesis we discuss the characterization of TFETs at low temperature. Si and SiGe homo- and hetero-junction TFETs fabricated by CEA-LETI (Grenoble, France) are considered with the objective to identify the possible presence of alternative injec- tion mechanisms such as Trap Assisted Tunneling.