Ferroelectric Negative Capacitance Transistors as Beyond Tunnel-FETs, Steep-Slope Devices: a Modeling, Simulation and Design Study

The IoT is one of the most trending businesses of modern times and has already opened a new world of opportunities for academic and industrial research. The IoT concept relies on a huge number of heterogeneous smart devices (i.e. $things$) that can communicate autonomously over the Internet, and also on a solid infrastructure to support the immense amount of datas continuously exchanged. Projections on the future of the IoT suggest a number of connected devices amply overcoming 50 billion within ten years, and with a predicted cost in terms of electricity consumption of over the 20% of the world energy demand.par In this context, IoT needs to be energy efficient under several aspects: for example by reducing the power consumption of each node of the smart grid and in the big data centers, and even by developing advanced software tools to nimbly manage the fluxes of informations. For these reasons different branches of electronic engineering can contribute to solve the overall efficiency issue.par This thesis addresses the problem from a nano-electronic perspective, analyzing possible solutions to limit the power dissipation in digital integrated circuits (ICs), in particular at the transistor level. In fact, in the last twenty years different strategies have been proposed to limit energy consumption in ICs but, due to some physical limitations of conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology, an effective solution is still missing.par The main avenue to lower power dissipation in ICs has been for years the reduction of supply voltage $V_{DD}$, according to a $Dennardian$ $scaling$, but for modern scaled devices this cannot be done anymore without encountering important drawbacks in terms of process, voltage and temperature (PVT) variability. This led to an era known as $Dark$ $Silicon$ age, where a substantial area of a chip is kept underclocked or underpowered to meet power constraints, thus meaning that the full potential performance cannot be exploited and a huge number of devices is wasted. This approach is clearly a palliative and becomes more and more inefficient at each technology node as the number of devices approximately doubles inside the chip, so that is has become important to improve the energy efficiency at transistor level.par To address the problem from a device perspective, we need to consider the two main contributions to the total enegy dissipation: the dynamic and the standby energy. The first contribution scales quadratically with $V_{DD}$, but at very low $V_{DD}$ the standby energy becomes the most critical contribution, which is related to the subthreshold-swing of the current-voltage relation: the steeper the characteristic is, the lower the leakage current. Unfortunately, the conventional CMOS technology has a limitation under this perspective due to the thermionic-emission transport mechanism that physically restricts the lowest possible swing.par The investigation of new device concepts that can overcome this limit is an active and challenging field of research for modern electronics, and two of the most interesting technologies in this sense are the $Tunnel$ $FET$ (TFET) and the $Negative$-$Capacitance$ transistor (NC-FET). In this thesis we focus on the promising NC-FET concept, which integrates $ferroelectric$ materials in the gate-stack to improve both the on- and the off-state performances of the transistor.par In this work we present an extensive study on the negative-capacitance feature in ferroelectrics, according to the Landau-Khalatnikov theory, and investigate several original designs for ferroelectric NC-FETs in order to reduce energy consumption in ICs. Moreover, a comparison against experiments is carried out in order to validate our results and in the last chapter the sensitivity of NC-FETs to temperature, process variations and interface defects are also examined.