Transfer-Matrix modeling of the Access Region Resistance in Graphene based Dirac-Source FETs

In this paper we first present a model based on the transfer-matrix methodology to describe the ballistic resistance in a graphene p–n junction, and employ the model in Dirac-Source FETs. In fact, the access region of a graphene based Dirac-Source FET includes a p–n junction, and we show that this has a sizeable impact on the on-state current of these transistors. In particular, we first validate our model by comparing the calculated p–n junction resistance with previous experiments and simulations. Then, we exploit the transfer-matrix description into a virtual- source model for nanoscale Dirac-Source FETs, and discuss the influence on the IDS -VGS curves of the p–n junction that is embedded in the access region of the device.