In CMOS technologies, rapidly becoming the most important ones for VLSI microelectronics, the inherent phenomenon of latch-up, represents one of the most serious limitations for further dimension scaling in the deep sub-micron range. For this reason latch-up has attracted a lot of attention in the last decade and a deep understanding of its essential features has been achieved, although a few specific problems are still to be satisfactorily solved.

Latch-up in CMOS circuits: a review

SANGIORGI, Enrico;SELMI, Luca;
1990-01-01

Abstract

In CMOS technologies, rapidly becoming the most important ones for VLSI microelectronics, the inherent phenomenon of latch-up, represents one of the most serious limitations for further dimension scaling in the deep sub-micron range. For this reason latch-up has attracted a lot of attention in the last decade and a deep understanding of its essential features has been achieved, although a few specific problems are still to be satisfactorily solved.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11390/687897
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