his paper and the companion work present the results of a comparative study between the tunnel-FETs (TFETs) and conventional MOSFETs for ultralow power digital circuits targeting a V-DD below 500 mV. For this purpose, we employed numerical TCAD simulations, as well as mixed device-circuit and lookup-table simulations using either the SENTAURUS or the Verilog-A environment. In particular, in this paper, we explore the device circuit interaction in n- and p-type TFETs, and propose a design leading to a good tradeoff between the current leakage and transistor imbalance at ultralow V-DD, as required in ultralow voltage systems. Then, we systematically compare the I-OFF, I-ON, effective capacitance, OFF-state and ON-state stacking factors for TFETs, SOI, and bulk MOSFETs in a wide range of V-DD. These results allow us to infer preliminary indications about the amenability for an aggressive voltage scaling of TFETs compared with MOSFETs, which will be further developed in the companion paper. We also report simulation results for the sensitivity of the transistors to the variation of some key device parameters. Even these process variation results set the stage for a more thorough investigation addressed in the companion paper about the limits imposed by process variability to voltage scaling for either TFETs or MOSFETs circuits.

Tunnel FETsfor Ultra-Low Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level

ESSENI, David;KAPIDANI, Bernard;ROLLO, TOMMASO;
2014-01-01

Abstract

his paper and the companion work present the results of a comparative study between the tunnel-FETs (TFETs) and conventional MOSFETs for ultralow power digital circuits targeting a V-DD below 500 mV. For this purpose, we employed numerical TCAD simulations, as well as mixed device-circuit and lookup-table simulations using either the SENTAURUS or the Verilog-A environment. In particular, in this paper, we explore the device circuit interaction in n- and p-type TFETs, and propose a design leading to a good tradeoff between the current leakage and transistor imbalance at ultralow V-DD, as required in ultralow voltage systems. Then, we systematically compare the I-OFF, I-ON, effective capacitance, OFF-state and ON-state stacking factors for TFETs, SOI, and bulk MOSFETs in a wide range of V-DD. These results allow us to infer preliminary indications about the amenability for an aggressive voltage scaling of TFETs compared with MOSFETs, which will be further developed in the companion paper. We also report simulation results for the sensitivity of the transistors to the variation of some key device parameters. Even these process variation results set the stage for a more thorough investigation addressed in the companion paper about the limits imposed by process variability to voltage scaling for either TFETs or MOSFETs circuits.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11390/1038014
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