We investigate the operation and performance of planar SiGe/Si and n0.53Ga0.47As/In0.7Ga0.3As/In0.53Ga0.47As hetero-junction Semiconductor on Insulator (ScOI) Tunnel FET (TFET) devices. The alignment between the hetero-junction, the gate edge and the source junction is systematically shifted to search for the highest ON-current and the lowest Subthreshold Swing (SS). A slight positive misalignment between the heterojunction and the metallurgical junction is beneficial to improve ION but for the considered devices the ON-current at VDD=0.5V and IOFF=1pA/m hardly exceeds 1A/m. Furthers reduction of the band gap by lattice strain appears mandatory to exceed this limit in the explored material systems.
On the Optimization of SiGe and III-V Compound Hetero-Junction Tunnel FET Devices
REVELANT, Alberto
Primo
;PALESTRI, Pierpaolo;OSGNACH, Patrik;LIZZIT, Daniel;SELMI, Luca
2013-01-01
Abstract
We investigate the operation and performance of planar SiGe/Si and n0.53Ga0.47As/In0.7Ga0.3As/In0.53Ga0.47As hetero-junction Semiconductor on Insulator (ScOI) Tunnel FET (TFET) devices. The alignment between the hetero-junction, the gate edge and the source junction is systematically shifted to search for the highest ON-current and the lowest Subthreshold Swing (SS). A slight positive misalignment between the heterojunction and the metallurgical junction is beneficial to improve ION but for the considered devices the ON-current at VDD=0.5V and IOFF=1pA/m hardly exceeds 1A/m. Furthers reduction of the band gap by lattice strain appears mandatory to exceed this limit in the explored material systems.| File | Dimensione | Formato | |
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