A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase-noise of ring oscillators consisting of MOS-current-mode-logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase-noise and power consumption is addressed.