Based on the material analysis of the SiN layers presented in part I of this paper, we develop accurate atomistic and electrical models for the silicon nitride (SiN)-based nonvolatile memory devices, taking into account the candidate SiN defects responsible for the memory effect. Our analysis points out the role of the hydrogen atoms and Si dangling bonds in the trapping properties of SiN films with different stoichiometries. The atomistic models provide a comprehensive picture describing the energy level and the occupation number of the different defects in the SiN. The electrical model coupled with the atomistic results, for the first time, demonstrates the ability to describe the program/erase curves of charge-trap memory cells with SiN storage layers with diversified composition. Good agreement between simulations and experimental results coming from the material analysis and the electrical characterization of thin (type-B device) and thick (type-A device) tunnel oxide memory cells is shown.

Explanation of the Charge Trapping Properties of Silicon Nitride Storage Layers for NVMs - Part II: Atomistic and Electrical Modeling

VIANELLO, Elisa;DRIUSSI, Francesco;PALESTRI, Pierpaolo;ESSENI, David;SELMI, Luca
2011-01-01

Abstract

Based on the material analysis of the SiN layers presented in part I of this paper, we develop accurate atomistic and electrical models for the silicon nitride (SiN)-based nonvolatile memory devices, taking into account the candidate SiN defects responsible for the memory effect. Our analysis points out the role of the hydrogen atoms and Si dangling bonds in the trapping properties of SiN films with different stoichiometries. The atomistic models provide a comprehensive picture describing the energy level and the occupation number of the different defects in the SiN. The electrical model coupled with the atomistic results, for the first time, demonstrates the ability to describe the program/erase curves of charge-trap memory cells with SiN storage layers with diversified composition. Good agreement between simulations and experimental results coming from the material analysis and the electrical characterization of thin (type-B device) and thick (type-A device) tunnel oxide memory cells is shown.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11390/878877
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