IRIS
DRIUSSI, Francesco
 Distribuzione geografica
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Continente #
NA - Nord America 6.943
EU - Europa 1.731
AS - Asia 743
AF - Africa 12
SA - Sud America 5
Continente sconosciuto - Info sul continente non disponibili 2
Totale 9.436
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Nazione #
US - Stati Uniti d'America 6.911
UA - Ucraina 449
IT - Italia 404
SG - Singapore 338
DE - Germania 299
CN - Cina 274
FI - Finlandia 161
IE - Irlanda 108
SE - Svezia 86
RU - Federazione Russa 73
TR - Turchia 73
FR - Francia 42
GB - Regno Unito 31
CA - Canada 29
BE - Belgio 19
VN - Vietnam 17
AT - Austria 13
IN - India 13
NL - Olanda 8
TG - Togo 8
HK - Hong Kong 5
RO - Romania 5
TW - Taiwan 5
ES - Italia 4
GR - Grecia 4
CH - Svizzera 3
CZ - Repubblica Ceca 3
DK - Danimarca 3
JP - Giappone 3
KR - Corea 3
BG - Bulgaria 2
IR - Iran 2
LT - Lituania 2
MA - Marocco 2
PE - Perù 2
PT - Portogallo 2
ZA - Sudafrica 2
A2 - ???statistics.table.value.countryCode.A2??? 1
AE - Emirati Arabi Uniti 1
AM - Armenia 1
AR - Argentina 1
AZ - Azerbaigian 1
BR - Brasile 1
CR - Costa Rica 1
EC - Ecuador 1
EU - Europa 1
HR - Croazia 1
HU - Ungheria 1
IS - Islanda 1
KG - Kirghizistan 1
KZ - Kazakistan 1
LA - Repubblica Popolare Democratica del Laos 1
LK - Sri Lanka 1
LU - Lussemburgo 1
MD - Moldavia 1
MK - Macedonia 1
MN - Mongolia 1
MX - Messico 1
NO - Norvegia 1
PA - Panama 1
PH - Filippine 1
PK - Pakistan 1
PL - Polonia 1
RS - Serbia 1
SK - Slovacchia (Repubblica Slovacca) 1
Totale 9.436
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Città #
Fairfield 1.002
Woodbridge 868
Houston 537
Chandler 516
Ann Arbor 507
Ashburn 460
Wilmington 394
Seattle 372
Cambridge 341
Jacksonville 293
Singapore 288
Dearborn 177
Udine 169
Boardman 157
Beijing 133
Dublin 106
Princeton 102
Izmir 69
San Diego 47
Dallas 33
Ogden 29
Santa Clara 29
Des Moines 25
Palaiseau 25
Ottawa 21
Hefei 20
Brussels 19
Helsinki 17
Dong Ket 16
Norwalk 16
Kunming 14
Bologna 13
Munich 13
Nanjing 12
Rome 12
Trieste 11
New York 10
Codroipo 9
Grafing 9
Redmond 9
Vienna 9
Guangzhou 8
Jinan 8
Lomé 8
Simi Valley 8
Martignacco 7
Frankfurt am Main 6
Modena 6
Nuremberg 6
Scafati 6
Horia 5
Lappeenranta 5
Los Angeles 5
Moscow 5
Parma 5
Shanghai 5
Taipei 5
Toronto 5
Zhengzhou 5
Barcelona 4
Hong Kong 4
Nürnberg 4
Paris 4
Redwood City 4
San Michele al Tagliamento 4
Shenyang 4
Zanica 4
Amsterdam 3
Andover 3
Brno 3
Chengdu 3
Chicago 3
Fuzhou 3
Indiana 3
London 3
Milan 3
Montreal 3
Nanchang 3
Phoenix 3
Quzhou 3
Sacile 3
Taizhou 3
Anzio 2
Auburn Hills 2
Augusta 2
Campoformido 2
Castelfranco Veneto 2
Cervignano Del Friuli 2
Chongqing 2
Copenhagen 2
Ferrara 2
Gatteo 2
Gemona 2
Hangzhou 2
Hebei 2
Hyderabad 2
Istanbul 2
Johannesburg 2
Kozhikode 2
Nanning 2
Totale 7.130
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Nome #
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors 170
Effects of Thermal Treatments on the Trapping Properties of HfO2 Films for Charge Trap Memories 166
New device concepts, transistor architectures and materials for high performance and energy efficient CMOS circuits in the forthcoming era of 3D integrated circuits 163
Backscattering and common-base current gain of the Graphene Base Transistor (GBT) 161
A New Expression for the Gain-Noise Relation of Single-Carrier Avalanche Photodiodes With Arbitrary Staircase Multiplication Regions 153
An Improved Nonlocal History-Dependent Model for Gain and Noise in Avalanche Photodiodes Based on Energy Balance Equation 149
Total Ionizing Dose Effects in Si-Based Tunnel FETs 145
Backscattering and common-base current gain of the Graphene Base Transistor (GBT) 140
Investigation of Hot Carrier Stress and Constant Voltage Stress in High-κ Si-Based TFETs 139
Influence of δ p-doping on the behaviour of GaAs/AlGaAs SAM-APDs for synchrotron radiation 137
Experimental characterization of the vertical position of the trapped charge in Si nitride-based nonvolatile memory cells 130
Going ballistic: Graphene hot electron transistors 130
Gain and noise in GaAs/AlGaAs avalanche photodiodes with thin multiplication regions 129
On the origin of the mobility reduction in n- and p-metal-oxide-semiconductor field effect transistors with hafnium-based/metal gate stacks 129
Experimental Characterization of Statistically Independent Defects in Gate Dielectrics - Part I: Description and Validation of the Model 128
Performance comparison for FinFETs, nanowire and stacked nanowires FETs: Focus on the influence of surface roughness and thermal effects 126
Simulation of DC and RF Performance of the Graphene Base Transistor 121
DFT study of graphene doping due to metal contacts 121
Experimental and Simulation Analysis of Program/Retention Transients in Silicon Nitride-Based NVM Cells 120
Hot Hole Gate Current in Surface Channel p-MOSFETs 120
Electrical Compact Modeling of Graphene Base Transistors 119
Improved understanding of metal–graphene contacts 118
A new Statistical Model to extract the Stress Induced Oxide Trap number and the Probability Density Distribution of the Gate Current Produced by a Single Trap 117
Impact of Device Layout and Annealing Process During the Passivation of Interface States in Presence of Silicon Nitride Layers 115
Benchmarking of 3-D MOSFET Architectures: Focus on the Impact of Surface Roughness and Self-Heating 114
A Quantitative Error Analysis of the Mobility Extraction According to the Matthiessen Rule in Advanced MOS Transistors 113
Explanation of SILC probability density distributions with nonuniform generation of traps in the tunnel oxide of flash memory arrays 113
On the Adequacy of the Transmission Line Model to Describe the Graphene-Metal Contact Resistance 113
Detailed characterization and critical discussion of series resistance in graphene-metal contacts 111
Explanation of the Charge-Trapping Properties of Silicon Nitride Storage Layers for NVM Devices Part I: Experimental Evidences From Physical and Electrical Characterizations 110
Graphene base transistors with bilayer tunnel barriers: Performance evaluation and design guidelines 110
On the Passivation of Interface States in SONOS Test Structures: Impact of Device Layout and Annealing Process 107
Investigation of the behaviour of GaAs/AlGaAs SAM-APDs for synchrotron radiation 107
Characterization and Modeling of long term retention in SONOS Non Volatile Memories 106
Graphene Base Transistors with optimized emitter and dielectrics 106
Analysis of nitride storage non-volatile memories with HfSiO(x) blocking dielectric and TiN metal gate for low power embedded applications 105
Semi-classical modeling of nanoscale nMOSFETs with III-V channel 105
Experimental procedure for accurate trap density study by low frequency charge pumping measurements 105
Long term charge retention dynamics of SONOS cells 104
Sub-1 nm Equivalent Oxide Thickness Al-HfO2 Trapping Layer with Excellent Thermal Stability and Retention for Nonvolatile Memory 104
Damage generation and location in n- and p-MOSFETs biased in the substrate-enhanced gate current regime 102
Reliability analysis of the metal-graphene contact resistance extracted by the transfer length method 102
An Improved Random Path Length Algorithm for p-i-n and Staircase Avalanche Photodiodes 101
Substrate enhanced degradation of cmos devices 100
Impact of bias conditions on electrical stress and ionizing radiation effects in Si-based TFETs 100
A Consistent Explanation of the Role of the SiN Composition on the Program/Retention Characteristics of MANOS and NROM like Memories 99
Fabrication, Characterization and Modeling of Strained SOI MOSFETs with Very Large Effective Mobility 99
Modeling, simulation and design of the vertical Graphene Base Transistor 99
Trade-off between Electron Velocity and Density of States in Ballistic nano-MOSFETs 98
Experimental Characterization of Statistically Independent Defects in Gate Dielectrics - Part II: Experimental Results on Flash Memory Arrays 98
Revised analysis of Coulomb scattering limited mobility in biaxially strained silicon MOSFETs 98
Direct Probing of Trapped Charge Dynamics in SiN by Kelvin Force Microscopy 92
Experimental and simulation study of the program efficiency of HfO2 based charge trapping memories 91
Impact of the Charge Transport in the Conduction Band on the Retention of Si-Nitride Based Memories 90
Modeling electrostatic doping and series resistance in graphene-FETs 89
Effects of electrical stress and ionizing radiation on Si-based TFETs 89
Optimization of GaAs/AlGaAs staircase avalanche photodiodes accounting for both electron and hole impact ionization 89
Does Multi Trap Assisted Tunneling Explain the Oxide Thickness Dependence of the Statistics of SILC in FLASH Memory Arrays ? 87
Comparison of modeling approaches for the capacitance-voltage and current voltage characteristics of advanced gate stacks 86
Analytical models for the insight into the use of alternative channel materials in ballistic nano-MOSFETs 85
New Charge Pumping model for the analysis of the spatial trap distribution in the nitride layer of SONOS devices 85
Programme and retention characteristics of SONOS memory arrays with layered tunnel barrier 84
Hot carrier degradation and damage profiling of cmos devices with biased substrates 83
New insight on the charge trapping mechanisms of SiN--based memory by atomistic simulations and electrical modeling 83
On the electron mobility enhancement in biaxially strained Si MOSFETs 81
Mobility extraction in SOI MOSFETs with sub 1 nm body thickness 80
Substrate Enhanced Gate Currents in CMOS Devices 78
Investigation of the Energy Distribution of Stress-Induced Oxide Traps by Numerical Analysis of the TAT of HEs 77
Mobility Extraction of UTB n-MOSFETs down to 0.9 nm SOI thickness 77
Performance, degradation monitors, and reliability of the CHISEL injection regime 76
Program efficiency and high temperature retention of SiN/high-K based memories 76
Observation of a new hole gate current component in p+-poly gate p-channel mosfet's 75
On the electrical monitor for device degradation in the CHISEL stress regime 74
Optimizing the Number of Steps and the Noise in Staircase APDs with Ternary III - V Semiconductor Alloys 74
Simulation Study of Coulomb Mobility in Strained Silicon 72
Experimental Extraction of Charge Centroid and of Charge Type in the P/E operation of SONOS Memory Cells 72
Simulations and Electrical Characterization of Double-side Double Type Column 3D Detectors 71
Effects of p doping on GaAs/AlGaAs SAM-APDs for X-rays detection 71
Gate Current in Stacked Dielectrics for Advanced FLASH EEPROM cells 68
Nitride Layer Influence on the Hydrogen Anneal of Interface Dangling Bonds 67
Modelling, simulation and design of the vertical Graphene Base Transistor 67
Explanation of the Charge Trapping Properties of Silicon Nitride Storage Layers for NVMs - Part II: Atomistic and Electrical Modeling 64
Simulation Study of the Trapping Properties of HfO2-Based Charge-Trap Memory Cells 64
Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies 61
Modelling and design of FTJs as multi-level low energy memristors for neuromorphic computing 59
Understanding the mobility reduction in MOSFETs featuring high-κ dielectrics 58
A simulation study of the Punch-through Assisted Hot Holes Injection mechanism for non-volatile-memory cells 56
Polarization switching and interface charges in BEOL compatible Ferroelectric Tunnel Junctions 56
Simulation Study of the Graphene Base Transistor 54
A model for the jitter of avalanche photodiodes with separate absorption and multiplication regions 53
Modelling and design of FTJs as high reading-impedance synaptic devices 49
Spectroscopic Analysis of Trap Assisted Tunneling on This Oxides by Means of Substrate Hot Electron Injection Experiments 41
Experimental and simulation analysis of carrier lifetimes in GaAs/AlGaAs Avalanche Photo-Diodes 41
Simulation study of Fermi level depinning in metal-MoS2 contacts 41
Dependability Assessment of Transfer Length Method to Extract the Metal–Graphene Contact Resistance 40
Versatile experimental setup for FTJ characterization 39
Dependable Contact Related Parameter Extraction in Graphene–Metal Junctions 39
Charge-Trapping-Induced Compensation of the Ferroelectric Polarization in FTJs: Optimal Conditions for a Synaptic Device Operation 37
Editorial: Letters from the 8th Joint International EUROSOI workshop and International Conference on Ultimate Integration on Silicon 35
Engineering of metal-MoS2 contacts to overcome Fermi level pinning 35
Totale 9.386
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Categoria #
all - tutte 37.270
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 37.270
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.286 0 0 0 0 0 0 294 311 256 204 74 147
2020/20211.408 45 149 95 194 73 197 53 140 168 75 129 90
2021/2022885 48 66 37 54 6 44 63 31 11 151 240 134
2022/20231.187 120 133 14 173 83 284 10 89 143 24 47 67
2023/2024474 54 30 42 7 55 34 23 37 45 31 24 92
2024/2025719 48 175 236 44 69 129 18 0 0 0 0 0
Totale 9.846